On Tue, 17 Jun 2008 18:34:39 -0400 Josh Boyer <[EMAIL PROTECTED]> wrote:
> A recent commit added support for the new 440x6 and 464 cores that have the > added WL1, IL1I, IL1D, IL2I, and ILD2 bits for the caching attributes in the > TLBs. The new bits were cleared in the finish_tlb_load function, however a > similar bit of code was missed in the DataStorage interrupt vector. > > Signed-off-by: Josh Boyer <[EMAIL PROTECTED]> Paul, this needs to go into 2.6.26. Do you have anything else queued up at the moment, or should I put this in my tree and ask Linus to pull it in? Sorry for the late fix. It was just noticed today. josh > --- > arch/powerpc/kernel/head_44x.S | 7 ++++++- > 1 files changed, 6 insertions(+), 1 deletions(-) > > diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S > index c2b9dc4..22b5d2c 100644 > --- a/arch/powerpc/kernel/head_44x.S > +++ b/arch/powerpc/kernel/head_44x.S > @@ -368,7 +368,12 @@ interrupt_base: > > rlwimi r11,r13,0,26,31 /* Insert static perms */ > > - rlwinm r11,r11,0,20,15 /* Clear U0-U3 */ > + /* > + * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added > + * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see > + * include/asm-powerpc/pgtable-ppc32.h for details). > + */ > + rlwinm r11,r11,0,20,10 > > /* find the TLB index that caused the fault. It has to be here. */ > tlbsx r10, 0, r10 _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
