Nice, thanks for reporting and testing. I submitted a qemu patch to hopefully avoid this happening again in future.
Thanks, Nick Excerpts from Christian Zigotzky's message of July 7, 2021 1:22 am: > Hi Nick, > > Your patch works (see patch below)! Many thanks for your help! We tested > it on an A-EON AmigaOne X5000/20 and in a virtual e5500 QEMU machine today. > > Screenshots: > > - > http://www.skateman.nl/wp-content/uploads/2021/07/Screenshot-at-2021-07-06-113237.png > - https://i.ibb.co/h813RRp/Kernel-5-14-alpha3-Power-PC.png > > Thanks, > Christian > > On 06 July 2021 at 06:07 am, Christian Zigotzky wrote: >> Hi Nick, >> >> Thanks a lot for your patch! We will test it as soon as possible. >> You're right that this issue doesn't exist in a virtual e5500 QEMU >> machine. >> >> Have a nice day, >> Christian >> >> On 06 July 2021 at 01:36 am, Nicholas Piggin wrote: >>> Excerpts from Christian Zigotzky's message of July 6, 2021 4:49 am: >>>> Hi All, >>>> >>>> Our FSL P50xx machines don't boot anymore because of IRQ issues. [1] >>>> >>>> Please check the IRQ changes in the latest PowerPC updates 5.14-1. [2] >>>> >>>> Thanks, >>>> Christian >>>> >>>> [1] >>>> https://forum.hyperion-entertainment.com/download/file.php?id=2592&mode=view >>>> >>>> >>>> [2] >>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=019b3fd94ba73d3ac615f0537440b81f129821f6 >>>> >>>> >>> This looks like mtmsrd in the 64e code. I think this should fix it. >>> >>> QEMU does not seem to trap on this, maybe something to improve. >>> >>> Thanks, >>> Nick >>> -- >>> >>> diff --git a/arch/powerpc/kernel/interrupt_64.S >>> b/arch/powerpc/kernel/interrupt_64.S >>> index 4063e8a3f704..d4212d2ff0b5 100644 >>> --- a/arch/powerpc/kernel/interrupt_64.S >>> +++ b/arch/powerpc/kernel/interrupt_64.S >>> @@ -311,9 +311,13 @@ END_BTB_FLUSH_SECTION >>> * trace_hardirqs_off(). >>> */ >>> li r11,IRQS_ALL_DISABLED >>> - li r12,-1 /* Set MSR_EE and MSR_RI */ >>> stb r11,PACAIRQSOFTMASK(r13) >>> +#ifdef CONFIG_PPC_BOOK3S >>> + li r12,-1 /* Set MSR_EE and MSR_RI */ >>> mtmsrd r12,1 >>> +#else >>> + wrteei 1 >>> +#endif >>> /* Calling convention has r9 = orig r0, r10 = regs */ >>> mr r9,r0 >> > >
