On Fri, 2 Apr 2021 12:41:24 +1000, Nicholas Piggin wrote:
> Starting with ISA v3.1, LPCR[AIL] no longer controls the interrupt
> mode for HV=1 interrupts. Instead, a new LPCR[HAIL] bit is defined
> which behaves like AIL=3 for HV interrupts when set.
>
> Set HAIL on bare metal to give us mmu-on interrupts and improve
> performance.
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors
https://git.kernel.org/powerpc/c/49c1d07fd04f54eb588c4a1dfcedc8d22c5ffd50
cheers
