Christophe Leroy <christophe.le...@csgroup.eu> writes:
> flush_coherent_icache() can use any valid address as mentionned
> by the comment.
>
> Use PAGE_OFFSET as base address. This allows removing the
> user access stuff.
>
> Signed-off-by: Christophe Leroy <christophe.le...@csgroup.eu>
> ---
> arch/powerpc/mm/mem.c | 13 +++++--------
> 1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
> index ce6c81ce4362..19f807b87697 100644
> --- a/arch/powerpc/mm/mem.c
> +++ b/arch/powerpc/mm/mem.c
> @@ -342,10 +342,9 @@ void free_initmem(void)
>
> /**
> * flush_coherent_icache() - if a CPU has a coherent icache, flush it
> - * @addr: The base address to use (can be any valid address, the whole cache
> will be flushed)
> * Return true if the cache was flushed, false otherwise
> */
> -static inline bool flush_coherent_icache(unsigned long addr)
> +static inline bool flush_coherent_icache(void)
> {
> /*
> * For a snooping icache, we still need a dummy icbi to purge all the
> @@ -355,9 +354,7 @@ static inline bool flush_coherent_icache(unsigned long
> addr)
> */
> if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
> mb(); /* sync */
> - allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
> - icbi((void *)addr);
> - prevent_read_from_user((const void __user *)addr,
> L1_CACHE_BYTES);
> + icbi((void *)PAGE_OFFSET);
> mb(); /* sync */
> isync();
> return true;
do we need that followup sync? Usermanual suggest sync; icbi(any address);
isync sequence.
-aneesh
