On Thu, Mar 25, 2021 at 10:01:35AM -0300, Arnaldo Carvalho de Melo wrote: > Em Wed, Mar 24, 2021 at 10:05:23AM +0530, Madhavan Srinivasan escreveu: > > > > On 3/22/21 8:27 PM, Athira Rajeev wrote: > > > Performance Monitoring Unit (PMU) registers in powerpc provides > > > information on cycles elapsed between different stages in the > > > pipeline. This can be used for application tuning. On ISA v3.1 > > > platform, this information is exposed by sampling registers. > > > Patch adds kernel support to capture two of the cycle counters > > > as part of perf sample using the sample type: > > > PERF_SAMPLE_WEIGHT_STRUCT. > > > > > > The power PMU function 'get_mem_weight' currently uses 64 bit weight > > > field of perf_sample_data to capture memory latency. But following the > > > introduction of PERF_SAMPLE_WEIGHT_TYPE, weight field could contain > > > 64-bit or 32-bit value depending on the architexture support for > > > PERF_SAMPLE_WEIGHT_STRUCT. Patches uses WEIGHT_STRUCT to expose the > > > pipeline stage cycles info. Hence update the ppmu functions to work for > > > 64-bit and 32-bit weight values. > > > > > > If the sample type is PERF_SAMPLE_WEIGHT, use the 64-bit weight field. > > > if the sample type is PERF_SAMPLE_WEIGHT_STRUCT, memory subsystem > > > latency is stored in the low 32bits of perf_sample_weight structure. > > > Also for CPU_FTR_ARCH_31, capture the two cycle counter information in > > > two 16 bit fields of perf_sample_weight structure. > > > > Changes looks fine to me. > > > > Reviewed-by: Madhavan Srinivasan <ma...@linux.ibm.com> > > So who will process the kernel bits? I'm merging the tooling parts,
I was sorta expecting these to go through the powerpc tree. Let me know if you want them in tip/perf/core instead.
