On May 30, 2008, at 1:49 AM, Wolfgang Grandegger wrote:
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash
memory and therefore a modified memory map is required and setup by
the board loader. This patch adds an appropriate DTS file.
Signed-off-by: Wolfgang Grandegger <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/tqm8548-bigflash.dts | 371 +++++++++++++++++++
+++++++++
1 files changed, 371 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/tqm8548-bigflash.dts
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/
powerpc/boot/dts/tqm8548-bigflash.dts
new file mode 100644
index 0000000..895bb80
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -0,0 +1,371 @@
+/*
+ * TQM8548 Device Tree Source
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2008 Wolfgang Grandegger <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as
published by the
+ * Free Software Foundation; either version 2 of the License, or
(at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "tqm,8548";
+ compatible = "tqm,8548", "tqm,85xx";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>; // from U-Boot
+ bus-frequency = <0>; // from U-Boot
+ clock-frequency = <0>; // from U-Boot
add next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0x0 0xa0000000 0x100000>;
+ reg = <0xa0000000 0x1000>; // CCSRBAR
+ bus-frequency = <0>;
+
+ [EMAIL PROTECTED] {
+ compatible = "fsl,8548-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ [EMAIL PROTECTED] {
add L2 label (L2 : l2-cache-...)
+ compatible = "fsl,8548-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+
+ mpic: [EMAIL PROTECTED] {
+ clock-frequency = <0>;
remove clock-frequency
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
remove big-endian.
+ };
+ };
+
- k
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
