Hi Nick, > +++ b/arch/powerpc/kvm/book3s_64_entry.S > @@ -0,0 +1,34 @@ > +#include <asm/cache.h> > +#include <asm/ppc_asm.h> > +#include <asm/kvm_asm.h> > +#include <asm/reg.h> > +#include <asm/asm-offsets.h> > +#include <asm/kvm_book3s_asm.h> > + > +/* > + * We come here from the first-level interrupt handlers. > + */ > +.global kvmppc_interrupt > +.balign IFETCH_ALIGN_BYTES > +kvmppc_interrupt: > + /* > + * Register contents:
Clearly r9 contains some data at this point, and I think it's guest r9 because of what you say later on in book3s_hv_rmhandlers.S::kvmppc_interrupt_hv. Is that right? Should that be documented in this comment as well? > + * R12 = (guest CR << 32) | interrupt vector > + * R13 = PACA > + * guest R12 saved in shadow VCPU SCRATCH0 > + * guest R13 saved in SPRN_SCRATCH0 > + */ > +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE > + std r9, HSTATE_SCRATCH2(r13) > + lbz r9, HSTATE_IN_GUEST(r13) > + cmpwi r9, KVM_GUEST_MODE_HOST_HV > + beq kvmppc_bad_host_intr > +#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE > + cmpwi r9, KVM_GUEST_MODE_GUEST > + ld r9, HSTATE_SCRATCH2(r13) > + beq kvmppc_interrupt_pr > +#endif > + b kvmppc_interrupt_hv > +#else > + b kvmppc_interrupt_pr > +#endif Apart from that I had a look and convinced myself that the code will behave the same as before. On that basis: Reviewed-by: Daniel Axtens <d...@axtens.net> Kind regards, Daniel
