* Gautham R. Shenoy <e...@linux.vnet.ibm.com> [2020-12-04 10:18:47]:
> From: "Gautham R. Shenoy" <e...@linux.vnet.ibm.com>
>
>
> Signed-off-by: Gautham R. Shenoy <e...@linux.vnet.ibm.com>
> ---
>
> +extern bool thread_group_shares_l2;
> /*
> * On big-core systems, each core has two groups of CPUs each of which
> * has its own L1-cache. The thread-siblings which share l1-cache with
> * @cpu can be obtained via cpu_smallcore_mask().
> + *
> + * On some big-core systems, the L2 cache is shared only between some
> + * groups of siblings. This is already parsed and encoded in
> + * cpu_l2_cache_mask().
> */
> static const struct cpumask *get_big_core_shared_cpu_map(int cpu, struct
> cache *cache)
> {
> if (cache->level == 1)
> return cpu_smallcore_mask(cpu);
> + if (cache->level == 2 && thread_group_shares_l2)
> + return cpu_l2_cache_mask(cpu);
>
> return &cache->shared_cpu_map;
As pointed with l...@intel.org, we need to do this only with #CONFIG_SMP,
even for cache->level = 1 too.
I agree that we are displaying shared_cpu_map correctly. Should we have also
update /clear shared_cpu_map in the first place. For example:- If for a P9
core with CPUs 0-7, the cache->shared_cpu_map for L1 would have 0-7 but
would display 0,2,4,6.
The drawback of this is even if cpus 0,2,4,6 are released L1 cache will not
be released. Is this as expected?
--
Thanks and Regards
Srikar Dronamraju
