> -----Original Message-----
> From: Kumar Gala [mailto:[EMAIL PROTECTED]
> Sent: Wednesday, May 21, 2008 11:39 AM
> To: Jin Zhengxiong
> Cc: linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH 3/4 V4] Enable MSI support for MPC8610HPCD board
>
>
> On May 20, 2008, at 10:29 PM, Jin Zhengxiong wrote:
>
> >
> >
> >> -----Original Message-----
> >> From: Kumar Gala [mailto:[EMAIL PROTECTED]
> >> Sent: Tuesday, May 20, 2008 9:24 PM
> >> To: Jin Zhengxiong
> >> Cc: linuxppc-dev@ozlabs.org
> >> Subject: Re: [PATCH 3/4 V4] Enable MSI support for
> MPC8610HPCD board
> >>
> >>> diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/
> >>> powerpc/platforms/86xx/mpc8610_hpcd.c
> >>> index dea1320..290d717 100644
> >>> --- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
> >>> +++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
> >>> @@ -71,9 +71,13 @@ static void __init mpc86xx_hpcd_init_irq(void)
> >>> /* Alloc mpic structure and per isu has 16 INT entries. */
> >>> mpic1 = mpic_alloc(np, res.start,
> >>> MPIC_PRIMARY | MPIC_WANTS_RESET |
> >> MPIC_BIG_ENDIAN,
> >>> - 0, 256, " MPIC ");
> >>> + 64, 256, " MPIC ");
> >>> BUG_ON(mpic1 == NULL);
> >>>
> >>> + mpic_assign_isu(mpic1, 0, res.start + 0x10000);
> >>> + mpic_assign_isu(mpic1, 1, res.start + 0x10800);
> >>> + mpic_assign_isu(mpic1, 2, res.start + 0x11600);
> >>> +
> >>
> >> I don't understand why you are breaking the interrupts up
> like this.
> >>
> >> If you leave as it was, the MSIs would start at hw irq 176
> >
> > If the ISU size is 0, mpic will only initialize the
> interrupt source
> > num reading from Feature Reporting Register(FRR), For 8610
> it's 104,
> > for 8572 it is 108, As the address space of the interrupt source
> > configuration register is not continuous(between
> 0xa00-0x1600), with
> > ISU=0, actually only the 16 externel interrupts and 64 internal
> > interrupts were initialized.
> > the Messaging interrupts and MSI interrupts were not intialized.
> >
> > With the original code. the Messaging interrupts would
> start at hwirq
> > 176 and the MSIs would
> > start at hwirq 224.
> > By setting the ISU=64, the Messaging interrupts would start
> at 128 and
> > the MSIs start at 176.
> > And all the interrupt sources will be initialized.
>
> Yeah, I remember this now. What about something like:
>
> diff --git a/arch/powerpc/sysdev/mpic.c
> b/arch/powerpc/sysdev/mpic.c index 8619f2a..90de869 100644
> --- a/arch/powerpc/sysdev/mpic.c
> +++ b/arch/powerpc/sysdev/mpic.c
> @@ -1251,6 +1251,8 @@ void __init mpic_init(struct mpic *mpic)
> if (mpic->irq_count == 0)
> mpic->irq_count = mpic->num_sources;
>
> + mpic->num_sources = max(mpic->num_sources, mpic->irq_count);
> +
> /* Do the HT PIC fixups on U3 broken mpic */
> DBG("MPIC flags: %x\n", mpic->flags);
> if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags &
> MPIC_PRIMARY)) {
>
Moving this code earlier to mpic_alloc like following patch, can make
mpic
initialize all the "irq_count" interrupt sources, although a little
difficult to understand
for those did not know the background.
On the other side, IF the reserved space was somewhat enlarged in the
source
configuration register, We need to enlarge the irq-count for those
unexist interrupts.
Jason
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 8619f2a..baa9df1 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1143,11 +1143,14 @@ struct mpic * __init mpic_alloc(struct
device_node *node,
greg_feature = mpic_read(mpic->gregs,
MPIC_INFO(GREG_FEATURE_0));
mpic->num_cpus = ((greg_feature &
MPIC_GREG_FEATURE_LAST_CPU_MASK)
>> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
- if (isu_size == 0)
+ if (isu_size == 0) {
mpic->num_sources =
((greg_feature &
MPIC_GREG_FEATURE_LAST_SRC_MASK)
>> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
+ mpic->num_sources = max(mpic->num_sources,
mpic->irq_count);
+ }
+
/* Map the per-CPU registers */
for (i = 0; i < mpic->num_cpus; i++) {
mpic_map(mpic, paddr, &mpic->cpuregs[i],
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