Excerpts from Christophe Leroy's message of November 7, 2020 6:15 pm: > > > Le 07/11/2020 à 04:23, Nicholas Piggin a écrit : >> ISA v2.06 (POWER7 and up) as well as e6500 support lbarx and lwarx. >> Add a compile option that allows code to use it, and add support in >> cmpxchg and xchg 8 and 16 bit values. > > Do you mean lharx ? Because lwarx exists on all powerpcs I think.
Thanks all who pointed out mistakes :) Yes lharx. > >> >> Signed-off-by: Nicholas Piggin <npig...@gmail.com> >> --- >> arch/powerpc/Kconfig | 3 + >> arch/powerpc/include/asm/cmpxchg.h | 236 ++++++++++++++++++++++++- >> arch/powerpc/platforms/Kconfig.cputype | 5 + >> 3 files changed, 243 insertions(+), 1 deletion(-) >> >> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig >> index e9f13fe08492..d231af06f75a 100644 >> --- a/arch/powerpc/Kconfig >> +++ b/arch/powerpc/Kconfig >> @@ -266,6 +266,9 @@ config PPC_BARRIER_NOSPEC >> default y >> depends on PPC_BOOK3S_64 || PPC_FSL_BOOK3E >> >> +config PPC_LBARX_LWARX >> + bool > > s/LWARX/LHARX/ ? > > And maybe better with PPC_HAS_LBARX_LWARX ? Yes you're right, PPC_HAS_ fits better. [...] >> +#endif > > That's a lot of code duplication. Could we use some macro, in the same spirit > as what is done in > arch/powerpc/include/asm/io.h for in_be16(), in_be32(), in_be64() and friends > ? For now I don't get too fancy. It's a bit ugly but I'm working through a generic atomics conversion patch and trying to also work out a nice form for larx/stcx operation generation macros, I'll look at tidying up this some time after then. Thanks, Nick
