Nothing prevent flush_cache_instruction() from behing writen in C. Do it to improve readability and maintainability.
Signed-off-by: Christophe Leroy <christophe.le...@csgroup.eu> --- arch/powerpc/kernel/misc_32.S | 13 ------------- arch/powerpc/mm/nohash/4xx.c | 15 +++++++++++++++ arch/powerpc/mm/nohash/Makefile | 1 + 3 files changed, 16 insertions(+), 13 deletions(-) create mode 100644 arch/powerpc/mm/nohash/4xx.c diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 4f4a31d9fdd0..87717966f5cd 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -268,19 +268,6 @@ _ASM_NOKPROBE_SYMBOL(real_writeb) #endif /* CONFIG_40x */ - -/* - * Flush instruction cache. - */ -#ifdef CONFIG_4xx -_GLOBAL(flush_instruction_cache) - lis r3, KERNELBASE@h - iccci 0,r3 - isync - blr -EXPORT_SYMBOL(flush_instruction_cache) -#endif - /* * Copy a whole page. We use the dcbz instruction on the destination * to reduce memory traffic (it eliminates the unnecessary reads of diff --git a/arch/powerpc/mm/nohash/4xx.c b/arch/powerpc/mm/nohash/4xx.c new file mode 100644 index 000000000000..954c8aa42a32 --- /dev/null +++ b/arch/powerpc/mm/nohash/4xx.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * This file contains the routines for initializing the MMU + * on the 4xx series of chips. + */ + +#include <asm/processor.h> +#include <asm/page.h> +#include <asm/cache.h> + +void flush_instruction_cache(void) +{ + iccci((void*)KERNELBASE); + isync(); +} diff --git a/arch/powerpc/mm/nohash/Makefile b/arch/powerpc/mm/nohash/Makefile index 0424f6ce5bd8..a7f7211b6373 100644 --- a/arch/powerpc/mm/nohash/Makefile +++ b/arch/powerpc/mm/nohash/Makefile @@ -4,6 +4,7 @@ ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC) obj-y += mmu_context.o tlb.o tlb_low.o obj-$(CONFIG_PPC_BOOK3E_64) += tlb_low_64e.o book3e_pgtable.o +obj-$(CONFIG_4xx) += 4xx.o obj-$(CONFIG_40x) += 40x.o obj-$(CONFIG_44x) += 44x.o obj-$(CONFIG_PPC_8xx) += 8xx.o -- 2.25.0