Hi Wolfram, >> + /* Begin transmission */ >> + setbits8(&i2c_reg->i2com, 0x80); > Hardcoded value. (I also wonder if 0x81 might be more suitable, as it > keeps the "be-a-master"-bit set. Still, both values work with my setup.)
>> +#ifdef I2C_CHIP_ERRATA >> + /* >> + * Chip errata, clear enable. This is not needed on rev D4 CPUs. >> + * Disabling I2C too early may cause too short stop condition >> + */ >> + udelay(4); >> + clrbits8(&i2c_reg->i2mod, 1); > I was unable to find the corresponding errata document, still I wonder > if it is a 0 which should have been written? The text says "clear" and > according to the reference manual, this means the bit should be 0. setbits8() and clrbits8() use a bitmask as second argument. setbits8(&i2c_reg->i2com, 0x80) will set bit 7 on the i2com register but leave bit 0 untouched. Likewise, clrbits8(&i2c_reg->i2mod, 1) will clear bit 0. Thanks, Jochen _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
