On Mon, 5 May 2008 08:53:19 +0200 Stefan Roese <[EMAIL PROTECTED]> wrote:
> The new 440x6 core used on AMCC 460EX/GT introduces new storage attibure > fields to the TLB2 word. Those are: > > Bit 11 12 13 14 15 > WL1 IL1I IL1D IL2I IL2D > > With these bits the cache (L1 and L2) can be configured in a more flexible > way, instruction- and data-cache independently now. The "old" I and W bits > are still available and setting these old bits will automically set these > new bits too (for backward compatibilty). > > The current code does not clear these fields resulting in disabling the cache > by chance. This patch now makes sure that these new bits are cleared when > the TLB2 word is written. > > Signed-off-by: Stefan Roese <[EMAIL PROTECTED]> Finally catching back up with email. This looks like .26 material, correct? josh _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
