On Mon, Jun 29, 2020 at 6:58 AM Aneesh Kumar K.V
<aneesh.ku...@linux.ibm.com> wrote:
>
> of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
> all previous writes are architecturally visible for the platform
> buffer flush.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.ibm.com>
> ---
> arch/powerpc/include/asm/cacheflush.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/powerpc/include/asm/cacheflush.h
> b/arch/powerpc/include/asm/cacheflush.h
> index 54764c6e922d..95782f77d768 100644
> --- a/arch/powerpc/include/asm/cacheflush.h
> +++ b/arch/powerpc/include/asm/cacheflush.h
> @@ -98,6 +98,13 @@ static inline void invalidate_dcache_range(unsigned long
> start,
> mb(); /* sync */
> }
>
> +#define arch_pmem_flush_barrier arch_pmem_flush_barrier
> +static inline void arch_pmem_flush_barrier(void)
> +{
> + if (cpu_has_feature(CPU_FTR_ARCH_207S))
> + asm volatile(PPC_PHWSYNC ::: "memory");
Shouldn't this fallback to a compatible store-fence in an else statement?
