Chris Packham <chris.pack...@alliedtelesis.co.nz> writes:
> Add the d-cache/i-cache properties for the T208x SoCs. The L1 cache on
> these SoCs is 32KiB and is split into 64 byte blocks (lines).
>
> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
> ---
> arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
LGTM.
I'll wait a few days to see if Scott wants to ack it.
cheers
> diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> index 3f745de44284..2ad27e16ac16 100644
> --- a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> @@ -81,6 +81,10 @@ cpus {
> cpu0: PowerPC,e6500@0 {
> device_type = "cpu";
> reg = <0 1>;
> + d-cache-line-size = <64>;
> + i-cache-line-size = <64>;
> + d-cache-size = <32768>;
> + i-cache-size = <32768>;
> clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x80000000>;
> @@ -88,6 +92,10 @@ cpu0: PowerPC,e6500@0 {
> cpu1: PowerPC,e6500@2 {
> device_type = "cpu";
> reg = <2 3>;
> + d-cache-line-size = <64>;
> + i-cache-line-size = <64>;
> + d-cache-size = <32768>;
> + i-cache-size = <32768>;
> clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x80000000>;
> @@ -95,6 +103,10 @@ cpu1: PowerPC,e6500@2 {
> cpu2: PowerPC,e6500@4 {
> device_type = "cpu";
> reg = <4 5>;
> + d-cache-line-size = <64>;
> + i-cache-line-size = <64>;
> + d-cache-size = <32768>;
> + i-cache-size = <32768>;
> clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x80000000>;
> @@ -102,6 +114,10 @@ cpu2: PowerPC,e6500@4 {
> cpu3: PowerPC,e6500@6 {
> device_type = "cpu";
> reg = <6 7>;
> + d-cache-line-size = <64>;
> + i-cache-line-size = <64>;
> + d-cache-size = <32768>;
> + i-cache-size = <32768>;
> clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x80000000>;
> --
> 2.25.1
