Haren Myneni's on March 19, 2020 4:14 pm: > > Alloc IRQ and get trigger port address for each VAS instance. Kernel > register this IRQ per VAS instance and sets this port for each send > window. NX interrupts the kernel when it sees page fault.
Again, should cc Cedric and Greg for XIVE / interrupt stuff. And for patch 2/14. The changelogs could use a bit of work. They're hard to read, and it can be a bit hard to decipher "why". Allocate a xive irq on each chip with a vas instance. The NX coprocessor raises a host CPU interrupt via vas if it encounters a page fault on an effective address. Subsequent patches register the trigger port with the NX coprocessor, and create a vas fault handler for this interrupt mapping. Don't know if the technical details are correct, but something like that in structure. Thanks, Nick
