Le 09/03/2020 à 09:57, Ravi Bangoria a écrit :
Future Power architecture is introducing second DAWR. Rename current
DAWR macros as:
  s/SPRN_DAWR/SPRN_DAWR0/
  s/SPRN_DAWRX/SPRN_DAWRX0/

I think you should tell that DAWR0 and DAWRX0 is the real name of the register as documented in (at least) power8 and power9 user manual.

Otherwise, we can't understand why you change the name of the register.

Christophe


Signed-off-by: Ravi Bangoria <ravi.bango...@linux.ibm.com>
---
  arch/powerpc/include/asm/reg.h          |  4 ++--
  arch/powerpc/kernel/dawr.c              |  4 ++--
  arch/powerpc/kvm/book3s_hv.c            | 12 ++++++------
  arch/powerpc/kvm/book3s_hv_rmhandlers.S | 18 +++++++++---------
  arch/powerpc/xmon/xmon.c                |  2 +-
  5 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index da5cab038e25..156ee89fa9be 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -283,14 +283,14 @@
  #define   CTRL_CT1    0x40000000      /* thread 1 */
  #define   CTRL_TE     0x00c00000      /* thread enable */
  #define   CTRL_RUNLATCH       0x1
-#define SPRN_DAWR      0xB4
+#define SPRN_DAWR0     0xB4
  #define SPRN_RPR      0xBA    /* Relative Priority Register */
  #define SPRN_CIABR    0xBB
  #define   CIABR_PRIV          0x3
  #define   CIABR_PRIV_USER     1
  #define   CIABR_PRIV_SUPER    2
  #define   CIABR_PRIV_HYPER    3
-#define SPRN_DAWRX     0xBC
+#define SPRN_DAWRX0    0xBC
  #define   DAWRX_USER  __MASK(0)
  #define   DAWRX_KERNEL        __MASK(1)
  #define   DAWRX_HYP   __MASK(2)
diff --git a/arch/powerpc/kernel/dawr.c b/arch/powerpc/kernel/dawr.c
index cc14aa6c4a1b..e91b613bf137 100644
--- a/arch/powerpc/kernel/dawr.c
+++ b/arch/powerpc/kernel/dawr.c
@@ -39,8 +39,8 @@ int set_dawr(struct arch_hw_breakpoint *brk)
        if (ppc_md.set_dawr)
                return ppc_md.set_dawr(dawr, dawrx);
- mtspr(SPRN_DAWR, dawr);
-       mtspr(SPRN_DAWRX, dawrx);
+       mtspr(SPRN_DAWR0, dawr);
+       mtspr(SPRN_DAWRX0, dawrx);
return 0;
  }
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 33be4d93248a..498c57e1f5c9 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -3383,8 +3383,8 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu 
*vcpu, u64 time_limit,
        int trap;
        unsigned long host_hfscr = mfspr(SPRN_HFSCR);
        unsigned long host_ciabr = mfspr(SPRN_CIABR);
-       unsigned long host_dawr = mfspr(SPRN_DAWR);
-       unsigned long host_dawrx = mfspr(SPRN_DAWRX);
+       unsigned long host_dawr = mfspr(SPRN_DAWR0);
+       unsigned long host_dawrx = mfspr(SPRN_DAWRX0);
        unsigned long host_psscr = mfspr(SPRN_PSSCR);
        unsigned long host_pidr = mfspr(SPRN_PID);
@@ -3413,8 +3413,8 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu *vcpu, u64 time_limit,
        mtspr(SPRN_SPURR, vcpu->arch.spurr);
if (dawr_enabled()) {
-               mtspr(SPRN_DAWR, vcpu->arch.dawr);
-               mtspr(SPRN_DAWRX, vcpu->arch.dawrx);
+               mtspr(SPRN_DAWR0, vcpu->arch.dawr);
+               mtspr(SPRN_DAWRX0, vcpu->arch.dawrx);
        }
        mtspr(SPRN_CIABR, vcpu->arch.ciabr);
        mtspr(SPRN_IC, vcpu->arch.ic);
@@ -3466,8 +3466,8 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu 
*vcpu, u64 time_limit,
              (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
        mtspr(SPRN_HFSCR, host_hfscr);
        mtspr(SPRN_CIABR, host_ciabr);
-       mtspr(SPRN_DAWR, host_dawr);
-       mtspr(SPRN_DAWRX, host_dawrx);
+       mtspr(SPRN_DAWR0, host_dawr);
+       mtspr(SPRN_DAWRX0, host_dawrx);
        mtspr(SPRN_PID, host_pidr);
/*
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S 
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index dbc2fecc37f0..f4b412b7cad8 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -707,8 +707,8 @@ BEGIN_FTR_SECTION
  END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
  BEGIN_FTR_SECTION
        mfspr   r5, SPRN_CIABR
-       mfspr   r6, SPRN_DAWR
-       mfspr   r7, SPRN_DAWRX
+       mfspr   r6, SPRN_DAWR0
+       mfspr   r7, SPRN_DAWRX0
        mfspr   r8, SPRN_IAMR
        std     r5, STACK_SLOT_CIABR(r1)
        std     r6, STACK_SLOT_DAWR(r1)
@@ -803,8 +803,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
        beq     1f
        ld      r5, VCPU_DAWR(r4)
        ld      r6, VCPU_DAWRX(r4)
-       mtspr   SPRN_DAWR, r5
-       mtspr   SPRN_DAWRX, r6
+       mtspr   SPRN_DAWR0, r5
+       mtspr   SPRN_DAWRX0, r6
  1:
        ld      r7, VCPU_CIABR(r4)
        ld      r8, VCPU_TAR(r4)
@@ -1772,8 +1772,8 @@ BEGIN_FTR_SECTION
         * If the DAWR doesn't work, it's ok to write these here as
         * this value should always be zero
        */
-       mtspr   SPRN_DAWR, r6
-       mtspr   SPRN_DAWRX, r7
+       mtspr   SPRN_DAWR0, r6
+       mtspr   SPRN_DAWRX0, r7
  END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
  BEGIN_FTR_SECTION
        ld      r5, STACK_SLOT_TID(r1)
@@ -2583,8 +2583,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
        mfmsr   r6
        andi.   r6, r6, MSR_DR          /* in real mode? */
        bne     4f
-       mtspr   SPRN_DAWR, r4
-       mtspr   SPRN_DAWRX, r5
+       mtspr   SPRN_DAWR0, r4
+       mtspr   SPRN_DAWRX0, r5
  4:    li      r3, 0
        blr
@@ -3340,7 +3340,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
        mtspr   SPRN_AMR, r0
        mtspr   SPRN_IAMR, r0
        mtspr   SPRN_CIABR, r0
-       mtspr   SPRN_DAWRX, r0
+       mtspr   SPRN_DAWRX0, r0
BEGIN_MMU_FTR_SECTION
        b       4f
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index e8c84d265602..6c4a8f8c0bd8 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -1938,7 +1938,7 @@ static void dump_207_sprs(void)
        printf("hfscr  = %.16lx  dhdes = %.16lx rpr    = %.16lx\n",
                mfspr(SPRN_HFSCR), mfspr(SPRN_DHDES), mfspr(SPRN_RPR));
        printf("dawr   = %.16lx  dawrx = %.16lx ciabr  = %.16lx\n",
-               mfspr(SPRN_DAWR), mfspr(SPRN_DAWRX), mfspr(SPRN_CIABR));
+               mfspr(SPRN_DAWR0), mfspr(SPRN_DAWRX0), mfspr(SPRN_CIABR));
  #endif
  }

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