maddy [ma...@linux.ibm.com] wrote: > > > __init_PMU: > > +#ifdef CONFIG_PPC_SVM > > + /* > > + * SVM's are restricted from accessing PMU, so skip. > > + */ > > + mfmsr r5 > > + rldicl r5, r5, 64-MSR_S_LG, 62 > > + cmpwi r5,1 > > + beq skip1 > > I know all MMCR* are loaded with 0. But > it is better if PEF code load the MMCR0 > with freeze bits on. I will send a separate > patch to handle in the non-svm case.
Quick question: By PEF code you mean the Ultravisor and not here in the SVM right? - bc SVMs cannot access PMU registers. > > Rest looks good. > Acked-by: Madhavan Srinivasan <ma...@linux.ibm.com> Cool, Thanks, Sukadev
