Segher Boessenkool <seg...@kernel.crashing.org> writes:
> On Thu, Nov 21, 2019 at 05:14:45PM +1100, Michael Ellerman wrote:
>> Christophe Leroy <christophe.le...@c-s.fr> writes:
>> That breaks 64-bit with GCC9:
>>
>> arch/powerpc/kernel/irq.c: In function 'do_IRQ':
>> arch/powerpc/kernel/irq.c:650:2: error: PIC register clobbered by 'r2' in
>> 'asm'
>> 650 | asm volatile(
>> | ^~~
>> arch/powerpc/kernel/irq.c: In function 'do_softirq_own_stack':
>> arch/powerpc/kernel/irq.c:711:2: error: PIC register clobbered by 'r2' in
>> 'asm'
>> 711 | asm volatile(
>> | ^~~
>>
>>
>> > diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
>> > index 04204be49577..d62fe18405a0 100644
>> > --- a/arch/powerpc/kernel/irq.c
>> > +++ b/arch/powerpc/kernel/irq.c
>> > @@ -642,6 +642,22 @@ void __do_irq(struct pt_regs *regs)
>> > irq_exit();
>> > }
>> >
>> > +static inline void call_do_irq(struct pt_regs *regs, void *sp)
>> > +{
>> > + register unsigned long r3 asm("r3") = (unsigned long)regs;
>> > +
>> > + /* Temporarily switch r1 to sp, call __do_irq() then restore r1 */
>> > + asm volatile(
>> > + " "PPC_STLU" 1, %2(%1);\n"
>> > + " mr 1, %1;\n"
>> > + " bl %3;\n"
>> > + " "PPC_LL" 1, 0(1);\n" :
>> > + "+r"(r3) :
>> > + "b"(sp), "i"(THREAD_SIZE - STACK_FRAME_OVERHEAD), "i"(__do_irq)
>> > :
>> > + "lr", "xer", "ctr", "memory", "cr0", "cr1", "cr5", "cr6", "cr7",
>> > + "r0", "r2", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11",
>> > "r12");
>> > +}
>>
>> If we add a nop after the bl, so the linker could insert a TOC restore,
>> then I don't think there's any circumstance under which we expect this
>> to actually clobber r2, is there?
>
> That is mostly correct.
That's the standard I aspire to :P
> If call_do_irq was a no-inline function, there would not be problems.
>
> What TOC does __do_irq require in r2 on entry, and what will be there
> when it returns?
The kernel TOC, and also the kernel TOC, unless something's gone wrong
or I'm missing something.
cheers
