Segher Boessenkool's on August 20, 2019 12:24 am:
> On Mon, Aug 19, 2019 at 01:58:12PM +0000, Christophe Leroy wrote:
>> -#define LOAD_REG_IMMEDIATE_SYM(reg,expr) \
>> - lis reg,(expr)@highest; \
>> - ori reg,reg,(expr)@higher; \
>> - rldicr reg,reg,32,31; \
>> - oris reg,reg,(expr)@__AS_ATHIGH; \
>> - ori reg,reg,(expr)@l;
>> +#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
>> + lis reg, (expr)@highest; \
>> + lis tmp, (expr)@__AS_ATHIGH; \
>> + ori reg, reg, (expr)@higher; \
>> + ori tmp, reg, (expr)@l; \
>> + rldimi reg, tmp, 32, 0
>
> That should be
>
> #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
> lis tmp, (expr)@highest; \
> ori tmp, tmp, (expr)@higher; \
> lis reg, (expr)@__AS_ATHIGH; \
> ori reg, reg, (expr)@l; \
> rldimi reg, tmp, 32, 0
>
> (tmp is the high half, reg is the low half, as inputs to that rldimi).
I guess the intention was also to try to fit the independent ops into
the earliest fetch/issue cycle possible.
#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
lis tmp, (expr)@highest; \
lis reg, (expr)@__AS_ATHIGH; \
ori tmp, tmp, (expr)@higher; \
ori reg, reg, (expr)@l; \
rldimi reg, tmp, 32, 0
Very cool series though.
Thanks,
Nick
