The patch fixes a bug, where the PESDRn_UTLSET1 register was setup
wrongly resulting in a non working PCIe port 1. With this fix both
PCIe ports work fine again.
Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
---
Based upon linux-next repo from 2008-03-31
arch/powerpc/sysdev/ppc4xx_pci.c | 10 ++++------
1 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 6c925b7..efaf4c4 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -785,19 +785,17 @@ static int ppc460ex_pciex_init_port_hw(struct
ppc4xx_pciex_port *port)
u32 val;
u32 utlset1;
- if (port->endpoint) {
+ if (port->endpoint)
val = PTYPE_LEGACY_ENDPOINT << 20;
- utlset1 = 0x20222222;
- } else {
+ else
val = PTYPE_ROOT_PORT << 20;
- utlset1 = 0x21222222;
- }
if (port->index == 0) {
val |= LNKW_X1 << 12;
+ utlset1 = 0x20000000;
} else {
val |= LNKW_X4 << 12;
- utlset1 |= 0x00101101;
+ utlset1 = 0x20101101;
}
mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
--
1.5.4.5
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