Michael Neuling <mi...@neuling.org> writes:
> When emulating tsr, treclaim and trechkpt, we incorrectly set CR0. The
> code currently sets:
> CR0 <- 00 || MSR[TS]
> but according to the ISA it should be:
> CR0 <- 0 || MSR[TS] || 0
Seems bad, what's the worst case impact?
Do we have a test case for this?
> This fixes the bit shift to put the bits in the correct location.
Fixes: ?
cheers
> diff --git a/arch/powerpc/kvm/book3s_hv_tm.c b/arch/powerpc/kvm/book3s_hv_tm.c
> index 888e2609e3..31cd0f327c 100644
> --- a/arch/powerpc/kvm/book3s_hv_tm.c
> +++ b/arch/powerpc/kvm/book3s_hv_tm.c
> @@ -131,7 +131,7 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
> }
> /* Set CR0 to indicate previous transactional state */
> vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
> - (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 28);
> + (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
> /* L=1 => tresume, L=0 => tsuspend */
> if (instr & (1 << 21)) {
> if (MSR_TM_SUSPENDED(msr))
> @@ -175,7 +175,7 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
>
> /* Set CR0 to indicate previous transactional state */
> vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
> - (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 28);
> + (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
> vcpu->arch.shregs.msr &= ~MSR_TS_MASK;
> return RESUME_GUEST;
>
> @@ -205,7 +205,7 @@ int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu)
>
> /* Set CR0 to indicate previous transactional state */
> vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
> - (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 28);
> + (((msr & MSR_TS_MASK) >> MSR_TS_S_LG) << 29);
> vcpu->arch.shregs.msr = msr | MSR_TS_S;
> return RESUME_GUEST;
> }
> --
> 2.21.0
