Hi Segher,

On 05/03/2019 06:15 PM, Segher Boessenkool wrote:
Hi Christophe,

On Fri, May 03, 2019 at 04:14:13PM +0200, Christophe Leroy wrote:
A while ago I proposed the following patch, and didn't get any comment
back on it.

I didn't see it.  Maybe because of holiday :-)

Thanks for this answer, I guess I'll drop it for the time being.

However, I've tried your suggestion below and get unnexpected result.

[...]



[ Btw.  Instead of

        __asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");

you can do

        __asm__ __volatile__ ("dcbf %0" : : "Z"(addr) : "memory");

to save some insns here and there. ]

Tried that change on dcbz() and checked function clear_page()

static inline void clear_page(void *addr)
{
        unsigned int i;

        for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
                dcbz(addr);
}

void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
{
        clear_page(page);

        /*
         * We shouldn't have to do this, but some versions of glibc
         * require it (ld.so assumes zero filled pages are icache clean)
         * - Anton
         */
        flush_dcache_page(pg);
}
EXPORT_SYMBOL(clear_user_page);


Before the change,

clear_user_page:
        mflr 0
        stw 0,4(1)
        bl _mcount
        stwu 1,-16(1)
        li 9,128
        mflr 0
        mtctr 9
        stw 0,20(1)
.L46:
#APP
 # 88 "./arch/powerpc/include/asm/cache.h" 1
        dcbz 0, 3
 # 0 "" 2
#NO_APP
        addi 3,3,32
        bdnz .L46
        lwz 0,20(1)
        mr 3,5
        mtlr 0
        addi 1,1,16
        b flush_dcache_page


After the change


clear_user_page:
        mflr 0
        stw 0,4(1)
        bl _mcount
        stwu 1,-32(1)
        li 9,128
        mflr 0
        mtctr 9
        stw 0,36(1)
.L46:
        stw 3,8(1)
        addi 9,1,8
#APP
 # 88 "./arch/powerpc/include/asm/cache.h" 1
        dcbz 0(9)
 # 0 "" 2
#NO_APP
        addi 3,3,32
        bdnz .L46
        mr 3,5
        bl flush_dcache_page
        lwz 0,36(1)
        addi 1,1,32
        mtlr 0
        blr


So first of all it uses an unexisting form of dcbz : "dcbz 0(9)"
And in addition, it stores r3 somewhere and I guess expects to read it with dcbz ???

Looks like 'Z' is not the right constraint to use.

Christophe

Reply via email to