On Wed, Mar 19, 2008 at 10:28:19AM -0500, Mike Hench wrote:
>
> From: Mike Hench
> Sent: Wednesday, March 19, 2008 10:22 AM
> To: '[EMAIL PROTECTED]'
> Subject: [PATCH] MPC813 NAND fixes
This patch is whitespace-mangled. Also, please don't post HTML.
> - unsigned int irq_status; /* status read from LTESR by irq
> handler */
>
> + volatile unsigned int irq_status; /* status read from LTESR
> by irq handler */
This change is not needed; both out_be32() and wait_event() act as
optimization barriers.
> @@ -379,13 +379,13 @@ static int fsl_elbc_run_command(struct m
>
> in_be32(&lbc->fbar), in_be32(&lbc->fpar),
>
> in_be32(&lbc->fbcr), priv->bank);
>
>
>
> + ctrl->irq_status = 0;
>
> /* execute special operation */
>
> out_be32(&lbc->lsor, priv->bank);
>
>
>
> /* wait for FCM complete flag or timeout */
>
> - ctrl->irq_status = 0;
ACK this change.
> wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
>
> - FCM_TIMEOUT_MSECS * HZ/1000);
>
> + (FCM_TIMEOUT_MSECS * HZ)/1000);
This change is a no-op. Multiplication and division are evaluated at the
same precedence, left-to-right.
> if (mtd->writesize == 512) {
>
> priv->page_size = 0;
>
> - clrbits32(&lbc->bank[priv->bank].or,
> ~OR_FCM_PGS);
>
> + clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
D'oh! Thanks for finding this.
ACK this change.
> - /* The default u-boot configuration on MPC8313ERDB causes
> errors;
>
> - * more delay is needed. This should be safe for other
> boards
>
> - * as well.
>
> - */
>
> - setbits32(&lbc->bank[priv->bank].or, 0x70);
And this one.
-Scott
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