On Wed, 2008-03-19 at 17:10 +1100, Michael Ellerman wrote: > The PCI bridge representing the PCIE root complex on Axon, contains device > BARs for a memory range and ROM that define inbound accesses. This confuses > the kernel resource management code, the resources need to be hidden when > Axon is a host bridge. > > Signed-off-by: Michael Ellerman <[EMAIL PROTECTED]> > ---
Acked-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]> _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
