On Fri, Sep 14, 2018 at 11:52:40AM +1000, Nicholas Piggin wrote:
> +
> +     /*
> +      * On POWER9, SRR1 bits do not match exactly as expected.
> +      * SRR1_WS_GPRLOSS (10b) can also result in SPR loss, so
> +      * always test PSSCR if there is any state loss.
> +      */
> +     if (likely((psscr & PSSCR_RL_MASK) < pnv_first_hv_loss_level)) {

Shouldn't we check PLS field to see if the cpu/core woke up from hv loss ?

Currently, a cpu requested stop4 (RL=4) and exited from a shallower state
(PLS=2), SPR's are unecessarily restored.

We can do something like : 

#define PSSCR_PLS_SHIFT         60
if (likely((psscr & PSSCR_PLS) >> PSSCR_PLS_SHIFT) < pnv_first_hv_loss_level)
> +             if (sprs_saved)
> +                     atomic_stop_thread_idle();
> +             goto out;
> +     }
> +
> +     /* HV state loss */
> +     BUG_ON(!sprs_saved);
> +
> +     atomic_lock_thread_idle();
> +
> +     if ((*state & ((1 << threads_per_core) - 1)) != 0)
> +             goto core_woken;
> +
> +     /* Per-core SPRs */
> +     mtspr(SPRN_PTCR,        sprs.ptcr);
> +     mtspr(SPRN_RPR,         sprs.rpr);
> +     mtspr(SPRN_TSCR,        sprs.tscr);
> +     mtspr(SPRN_LDBAR,       sprs.ldbar);
> +     mtspr(SPRN_AMOR,        sprs.amor);
> +
> +     if ((psscr & PSSCR_RL_MASK) >= pnv_first_tb_loss_level) {
> +             /* TB loss */
> +             if (opal_resync_timebase() != OPAL_SUCCESS)
> +                     BUG();
> +     }


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