The following bits in the GUMR is changed for non
tsa mode: CDS, CTSP and CTSS are set to zero.

When set, there is no tx interrupts from the controller.

Signed-off-by: David Gounaris <david.gouna...@infinera.com>
---
 drivers/net/wan/fsl_ucc_hdlc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index 3dacafb219c6..999d93fa54f7 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -97,6 +97,12 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
        if (priv->tsa) {
                uf_info->tsa = 1;
                uf_info->ctsp = 1;
+               uf_info->cds = 1;
+               uf_info->ctss = 1;
+       } else {
+               uf_info->cds = 0;
+               uf_info->ctsp = 0;
+               uf_info->ctss = 0;
        }
 
        /* This sets HPM register in CMXUCR register which configures a
-- 
2.13.6

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