> -----Original Message-----
> From: linux-kernel-ow...@vger.kernel.org <linux-kernel-
> ow...@vger.kernel.org> On Behalf Of Scott Wood
> Sent: Wednesday, August 29, 2018 5:49 AM
> To: Vabhav Sharma <vabhav.sha...@nxp.com>; linux-
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> Cc: Yogesh Narayan Gaur <yogeshnarayan.g...@nxp.com>; Andy Tang
> <andy.t...@nxp.com>; Udit Kumar <udit.ku...@nxp.com>;
> li...@armlinux.org.uk; Varun Sethi <v.se...@nxp.com>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
>
> On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > From: Yogesh Gaur <yogeshnarayan.g...@nxp.com>
> >
> > Add clockgen support for lx2160a.
> > Added entry for compat 'fsl,lx2160a-clockgen'.
> > As LX2160A is 16 core, so modified value for NUM_CMUX
> >
> > Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.g...@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sha...@nxp.com>
> > ---
> > drivers/clk/clk-qoriq.c | 14 +++++++++++++-
> > drivers/cpufreq/qoriq-cpufreq.c | 1 +
> > 2 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > 3a1812f..fc6e308 100644
> > --- a/drivers/clk/clk-qoriq.c
> > +++ b/drivers/clk/clk-qoriq.c
> > @@ -60,7 +60,7 @@ struct clockgen_muxinfo { };
> >
> > #define NUM_HWACCEL 5
> > -#define NUM_CMUX 8
> > +#define NUM_CMUX 16
> >
> > struct clockgen;
> >
> > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
> > .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > },
> > {
> > + .compat = "fsl,lx2160a-clockgen",
> > + .cmux_groups = {
> > + &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > + },
> > + .cmux_to_group = {
> > + 0, 0, 0, 0, 1, 1, 1, 1, -1
> > + },
> > + .pll_mask = 0x37,
> > + .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > + },
>
> Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8
> entries in cmux_to_group?
Configuration is 16 cores,8 cluster with 2 cores in each cluster
>
> -Scott
