On Sun, 10 Jun 2018 22:58:11 +0200
Michal Suchánek <msucha...@suse.de> wrote:
> On Sun, 10 Jun 2018 23:30:27 +1000
> Nicholas Piggin <npig...@gmail.com> wrote:
>
> > POWER9 DD1 was never a product. It is no longer supported by upstream
> > firmware, and it is not effectively supported in Linux due to lack of
> > testing.
> >
>
> > diff --git a/arch/powerpc/kvm/book3s_xive_template.c
> > b/arch/powerpc/kvm/book3s_xive_template.c index
> > 99c3620b40d9..487f1f6650cc 100644 ---
> > a/arch/powerpc/kvm/book3s_xive_template.c +++
> > b/arch/powerpc/kvm/book3s_xive_template.c @@ -25,18 +25,6 @@ static
> > void GLUE(X_PFX,ack_pending)(struct kvmppc_xive_vcpu *xc) */
> > eieio();
> >
> > - /*
> > - * DD1 bug workaround: If PIPR is less favored than CPPR
> > - * ignore the interrupt or we might incorrectly lose an IPB
> > - * bit.
> > - */
> > - if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
> > - __be64 qw1 = __x_readq(__x_tima + TM_QW1_OS);
> > - u8 pipr = be64_to_cpu(qw1) & 0xff;
> > - if (pipr >= xc->hw_cppr)
> > - return;
> > - }
> > -
> > /* Perform the acknowledge OS to register cycle. */
> > ack = be16_to_cpu(__x_readw(__x_tima + TM_SPC_ACK_OS_REG));
> >
> > @@ -105,7 +93,7 @@ static void GLUE(X_PFX,source_eoi)(u32 hw_irq,
> > struct xive_irq_data *xd) *
> > * For LSIs, using the HW EOI cycle works around a
> > problem
> > * on P9 DD1 PHBs where the other ESB accesses don't
> > work
> > - * properly.
> > + * properly. XXX: can this be removed?
> > */
> > if (xd->flags & XIVE_IRQ_FLAG_LSI)
> > __x_readq(__x_eoi_page(xd) +
>
> Maybe this should be really removed or the comment changed to why it is
> still useful?
Good point, I meant to ask Ben about that.
Thanks,
Nick
