On 04/26/2018 11:27 PM, Michael Ellerman wrote:
> Haren Myneni <ha...@linux.vnet.ibm.com> writes:
>>
>> NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
>> which is not used for paste return value. So. mask this bit to get
>> proper return status.
>
> This sounds like a bug fix, but I can't tell from the change log.
>
> What happens if we don't merge this patch? Is it bad?
>
> Should I add:
>
> Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
> Cc: sta...@vger.kernel.org # v4.14+
Thanks for your review.
Yes, it is a bug, We should ignore XER[SO] from the return status which is
nothing to with NX. Otherwise, successful paste instruction will be returned as
failure when this bit is set. Not easy to reproduce. We did not see this bug on
P9 NX 842 so far, but noticed this issue few times when testing user space NX
gzip with 32 threads and 1 million requests per thread. We added similar fix on
P8 (with icswx) and can happen on P9 NX842.
P8 fix - 6333ed8f26cf crypto: nx-842 - Mask XERS0 bit in return value
paste (powerISA V3.0b page#855):
CR0 Description
0b000||XERSO Data transfer failed due to a
sequence error or a conflict with
tlbie or some implementation-
specific problem.
0b001||XERSO Data transfer successful
I will resend patch with more description.
Thanks
Haren
>
>
> cheers
>
>> diff --git a/arch/powerpc/platforms/powernv/copy-paste.h
>> b/arch/powerpc/platforms/powernv/copy-paste.h
>> index c9a5036..82392e3 100644
>> --- a/arch/powerpc/platforms/powernv/copy-paste.h
>> +++ b/arch/powerpc/platforms/powernv/copy-paste.h
>> @@ -9,7 +9,8 @@
>> #include <asm/ppc-opcode.h>
>>
>> #define CR0_SHIFT 28
>> -#define CR0_MASK 0xF
>> +#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */
>> +
>> /*
>> * Copy/paste instructions:
>> *
>
