On Tue, 2018-02-13 at 05:51:35 UTC, Alexey Kardashevskiy wrote: > GPUs and the corresponding NVLink bridges get different PEs as they have > separate translation validation entries (TVEs). We put these PEs to > the same IOMMU group so they cannot be passed through separately. > So the iommu_table_group_ops::set_window/unset_window for GPUs do set > tables to the NPU PEs as well which means that iommu_table's list of > attached PEs (iommu_table_group_link) has both GPU and NPU PEs linked. > This list is used for TCE cache invalidation. > > The problem is that NPU PE has just a single TVE and can be programmed > to point to 32bit or 64bit windows while GPU PE has two (as any other PCI > device). So we end up having an 32bit iommu_table struct linked to both > PEs even though only the 64bit TCE table cache can be invalidated on NPU. > And a relatively recent skiboot detects this and prints errors. > > This changes GPU's iommu_table_group_ops::set_window/unset_window to make > sure that NPU PE is only linked to the table actually used by the hardware. > If there are two tables used by an IOMMU group, the NPU PE will use > the last programmed one which with the current use scenarios is expected > to be a 64bit one. > > Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru>
Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/d41ce7b1bcc3e1d02cc9da3b83c0fe cheers
