From: Simon Guo <wei.guo.si...@gmail.com>
MSR TS bits can be modified with non-privileged instruction like
tbegin./tend. That means guest can change MSR value "silently" without
notifying host.
It is necessary to sync the TM bits to host so that host can calculate
shadow msr correctly.
note privilege guest will always fail transactions so we only take
care of problem state guest.
Signed-off-by: Simon Guo <wei.guo.si...@gmail.com>
Reviewed-by: Paul Mackerras <pau...@ozlabs.org>
---
arch/powerpc/kvm/book3s_pr.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 4e9acdd..7ec866a 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -977,6 +977,9 @@ int kvmppc_handle_exit_pr(struct kvm_run *run, struct
kvm_vcpu *vcpu,
{
int r = RESUME_HOST;
int s;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ ulong old_msr = kvmppc_get_msr(vcpu);
+#endif
vcpu->stat.sum_exits++;
@@ -988,6 +991,28 @@ int kvmppc_handle_exit_pr(struct kvm_run *run, struct
kvm_vcpu *vcpu,
trace_kvm_exit(exit_nr, vcpu);
guest_exit();
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ /*
+ * Unlike other MSR bits, MSR[TS]bits can be changed at guest without
+ * notifying host:
+ * modified by unprivileged instructions like "tbegin"/"tend"/
+ * "tresume"/"tsuspend" in PR KVM guest.
+ *
+ * It is necessary to sync here to calculate a correct shadow_msr.
+ *
+ * privileged guest's tbegin will be failed at present. So we
+ * only take care of problem state guest.
+ */
+ if (unlikely((old_msr & MSR_PR) &&
+ (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) !=
+ (old_msr & (MSR_TS_MASK)))) {
+ old_msr &= ~(MSR_TS_MASK);
+ old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK));
+ kvmppc_set_msr_fast(vcpu, old_msr);
+ kvmppc_recalc_shadow_msr(vcpu);
+ }
+#endif
+
switch (exit_nr) {
case BOOK3S_INTERRUPT_INST_STORAGE:
{
--
1.8.3.1
