Hi Maciej,
On Mon, Nov 27, 2017 at 11:34:44PM +0100, Maciej S. Szmigiero wrote:
> There is no problem in using different bit widths in playback and capture
> in AC'97 mode so allow this, too.
> @@ -1557,11 +1558,12 @@ static int fsl_ssi_probe(struct platform_device *pdev)
>
> /* Are the RX and the TX clocks locked? */
> if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
> - if (!fsl_ssi_is_ac97(ssi_private))
> + if (!fsl_ssi_is_ac97(ssi_private)) {
> ssi_private->cpu_dai_drv.symmetric_rates = 1;
> + ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
> + }
>
> ssi_private->cpu_dai_drv.symmetric_channels = 1;
> - ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
> }
I was actually wondering how the AC97 works in the synchronous mode
while being able to handle different bit widths. Then I found that
the drivers does corresponding configurations for synchronous mode
only if symmetric_rates is set -- which is unset for AC97 cases. So
in fact AC97 case (symmetric_rates unset) is probably being treated
as asynchronous mode by the driver -- it'd be better if you confirm
this for me.
And I am not so sure about the physical pin connections in an AC97
situation, but I started to think that, instead of having a change
above, AC97 cases might be supposed to have "fsl,ssi-asynchronous"
property in DT since it's working when the driver sets both TX and
RX control registers (i.e. asynchronous mode), not like synchronous
mode that only sets TX's registers.
Thanks
Nicolin
