On Feb 1, 2008, at 1:54 AM, David Gibson wrote:
> On Thu, Jan 24, 2008 at 06:41:24PM -0500, Paul Gortmaker wrote:
>> This adds a v1 device tree source for the Wind River SBC8560
>> board. The
>> biggest difference between this and the MPC8560ADS reference platform
>> dts is the use of an external 16550 compatible UART instead of the
>> CPM2.
>>
>> Signed-off-by: Paul Gortmaker <[EMAIL PROTECTED]>
>
> [snip]
>> +/dts-v1/;
>> +
>> +/ {
>> + model = "SBC8560";
>> + compatible = "SBC8560";
>
> This is not the conventional format for board-level compatible
> entries, which should generally be "vendor,model" and all in lower
> case.
>
> [snip]
>> + enet0: [EMAIL PROTECTED] {
>> + cell-index = <0>;
>> + device_type = "network";
>> + model = "TSEC";
>> + compatible = "gianfar";
>
> This looks like the old dodgy gianfar binding, and needs updating
> (mdio node will probably also need changes).
>
> [snip]
>> + [EMAIL PROTECTED] {
>> + compatible = "fsl,mpc8560-localbus";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + reg = <0xff705000 0x100>; // BRx, ORx, etc.
>> +
>> + ranges = <
>> + 0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
>> + 0x1 0x0 0xe4000000 0x4000000 // 64MB flash
>> + 0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
>> + 0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
>> + 0x5 0x0 0xfc000000 0x0c00000 // EPLD
>> + 0x6 0x0 0xe0000000 0x4000000 // 64MB flash
>> + 0x7 0x0 0x80000000 0x0200000 // ATM1,2
>> + >;
>> +
>> + [EMAIL PROTECTED],0 {
>
> I'm not entirely convinced on this two-level representation. I think
> the FSL people need to get together and define a binding (or set of
> bindings) for their various chipselect style external bus bridges.
It seems reasonable if you had a FPGA off of the localbus to have a
two level representation. One for the localbus controller on the FSL
part and the child to describe the FPGA.
What are you expecting beyond what we have today? I guess I'm asking
what's missing from the localbus nodes we have?
- k
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