On Tue, 2017-10-24 at 13:06:54 UTC, Nicholas Piggin wrote: > According to the architecture, the process table entry cache must be > flushed with tlbie RIC=2. > > Currently the process table entry is set to invalid right before the > PID is returned to the allocator, with no invalidation. This works on > existing implementations that are known to not cache the process table > entry for any except the current PIDR. > > It is architecturally correct and cleaner to invalidate with RIC=2 > after clearing the process table entry and before the PID is returned > to the allocator. This can be done in arch_exit_mmap that runs before > the final flush, and to ensure the final flush (fullmm) is always a > RIC=2 variant. > > Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/30b49ec798f0984b905fd94d1957d6 cheers
