Josh Boyer wrote:
> On Wed, 23 Jan 2008 23:37:33 +0100
> Roel Kluin <[EMAIL PROTECTED]> wrote:
>
>> logical/bitand typo
>>
>> Signed-off-by: Roel Kluin <[EMAIL PROTECTED]>
>> ---
>> diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
>> index ebf9e21..dcfb459 100644
>> --- a/arch/powerpc/boot/4xx.c
>> +++ b/arch/powerpc/boot/4xx.c
>> @@ -104,7 +104,7 @@ void ibm4xx_denali_fixup_memsize(void)
>> val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
>> cs = 0;
>> while (val) {
>> - if (val && 0x1)
>> + if (val & 0x1)
>> cs++;
>> val = val >> 1;
>> }
>
> Hm, good catch.
Yes, thanks!
Sequoia and Rainier are currently the only boards using denali
controller and have both chipselects enabled (val = 0x3).
In this case the problem doesn't show up and we still get the right cs
value.
Thanks,
Valentine.
>
> Stefan, have you had problems with this code at all?
>
> josh
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