On Thu, Aug 24, 2017 at 04:37:49PM -0400, Roy Pledge wrote: > From: Claudiu Manoil <claudiu.man...@nxp.com> > > Not relevant and arch dependent. Overkill for PPC. > > Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com> > Signed-off-by: Roy Pledge <roy.ple...@nxp.com> > --- > drivers/soc/fsl/qbman/dpaa_sys.h | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h > b/drivers/soc/fsl/qbman/dpaa_sys.h > index 2ce394a..f85c319 100644 > --- a/drivers/soc/fsl/qbman/dpaa_sys.h > +++ b/drivers/soc/fsl/qbman/dpaa_sys.h > @@ -49,10 +49,6 @@ > #define DPAA_PORTAL_CE 0 > #define DPAA_PORTAL_CI 1 > > -#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64) > -#error "Unsupported Cacheline Size" > -#endif
Maybe this check was for a reason on PPC as it uses WB memory mappings for some of the qbman descriptors (which IIUC fit within a cacheline). You could add a check for CONFIG_PPC if you think there is any chance of this constant going higher. -- Catalin
