All, On Wed, Jun 28, 2017 at 11:30 AM, Matthew Weber <matthew.we...@rockwellcollins.com> wrote: > Scott, > > On Sun, Apr 30, 2017 at 2:01 AM, Scott Wood <o...@buserror.net> wrote: >> On Thu, Apr 27, 2017 at 12:59:40PM -0500, Matt Weber wrote: >>> This patch updates the machine check handler of Linux kernel to >>> handle the e6500 architecture case. In e6500 core, L1 Data Cache Write >>> Shadow Mode (DCWS) register is not implemented but L1 data cache always >>> runs in write shadow mode. So, on L1 data cache parity errors, hardware >>> will automatically invalidate the data cache but will still log a >>> machine check interrupt. >>> >>> Signed-off-by: Ronak Desai <ronak.de...@rockwellcollins.com> >>> Signed-off-by: Matthew Weber <matthew.we...@rockwellcollins.com> > > <snip> > > Sent a v2 this morning, sorry about the delay. > https://patchwork.ozlabs.org/patch/781763/ >
Checking on this older patch, anything else needed for merge? Matt
