On Thu, 2017-07-06 at 10:51:28 UTC, Nicholas Piggin wrote: > There are two cases outside the normal address space management > where a CPU's local TLB is to be flushed: > > 1. Host boot; in case something has left stale entries in the > TLB (e.g., kexec). > > 2. Machine check; to clean corrupted TLB entries. > > CPU state restore from deep idle states also flushes the TLB. > However this seems to be a side effect of reusing the boot code to set > CPU state, rather than a requirement itself. > > The current flushing has a number of problems with ISA v3.0B: > > - The current radix mode of the MMU is not taken into account. tlbiel > is undefined if the R field does not match the current radix mode. > > - ISA v3.0B hash must flush the partition and process table caches. > > - ISA v3.0B radix must flush partition and process scoped translations, > partition and process table caches, and also the page walk cache. > > Add POWER9 cases to handle these, with radix vs hash determined by the > host MMU mode. > > Signed-off-by: Nicholas Piggin <npig...@gmail.com> > Reviewed-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com>
Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/41d0c2ecde19cfe93071ed7b979a53 cheers
