On Mon, 24 Apr 2017 15:09:02 +1000 Benjamin Herrenschmidt <b...@kernel.crashing.org> wrote:
> On Mon, 2017-04-24 at 14:55 +1000, Nicholas Piggin wrote: > > On Mon, 24 Apr 2017 11:47:48 +1000 > > > Benjamin Herrenschmidt <b...@kernel.crashing.org> wrote: > > > > > On Thu, 2017-03-30 at 22:10 +1000, Nicholas Piggin wrote: > > > > There are some windows in opal entry/exit that can not recover from a > > > > re-entrant interrupt (e.g., machine check) due to using SRR registers, > > > > but they currently do not have MSR_RI clear. > > > > > > > > These were found by machine check injection coverage tests using the > > > > powerpc system simulator (Mambo). > > > > > > So you make us enter/exit OPAL with RI off with your patch. > > > > It should hrfid to opal with MSR_RI set. It seems to be doing the right > > thing when stepping through it with the simulator. > > Ok, it's me mis-reading it... > > I am not fan of changing FIXUP_ENDIAN but I suppose we don't have much > choice. This will slow down OPAL entry/exit further...maybe we should > use HSRR0/1 instead ? That way we don't have to touch RI ... I'll see if I can make that work.
