Minimal tree for mpc5121 ads.
Signed-off-by: John Rigby <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/mpc5121ads.dts | 116 ++++++++++++++++++++++++++++++++++
1 files changed, 116 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc5121ads.dts
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts
b/arch/powerpc/boot/dts/mpc5121ads.dts
new file mode 100644
index 0000000..fac1f15
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -0,0 +1,116 @@
+/*
+ * MPC5121E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "MPC5121ADS";
+ compatible = "fsl,mpc5121ads";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>; // 32 bytes
+ i-cache-line-size = <20>; // 32 bytes
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <d#49500000>; // 49.5 MHz (csb/4)
+ bus-frequency = <d#198000000>; // 198 MHz csb bus
+ clock-frequency = <d#396000000>;// 396 MHz ppc core
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 10000000>; // 256MB at 0
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "fsl,mpc5121ads_localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <80000020 40>;
+
+ ranges = <0 0 fc000000 04000000
+ 2 0 82000000 00008000>;
+
+ [EMAIL PROTECTED],0 {
+ compatible = "cfi-flash";
+ reg = <0 0 4000000>;
+ bank-width = <4>;
+ device-width = <1>;
+ };
+
+ [EMAIL PROTECTED],0 {
+ compatible = "fsl,mpc5121ads-cpld";
+ reg = <2 0 8000>;
+ };
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "fsl,mpc5121-immr";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ ranges = <0 80000000 400000>;
+ reg = <80000000 400000>;
+ bus-frequency = <d#66000000>; // 66 MHz ips bus
+
+
+ // IPIC
+ // interrupts cell = <intr #, sense>
+ // sense values match linux IORESOURCE_IRQ_* defines:
+ // sense == 8: Level, low assertion
+ // sense == 2: Edge, high-to-low change
+ //
+ ipic: [EMAIL PROTECTED] {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <c00 100>;
+ };
+
+ // 512x PSCs are not 52xx PSCs compatible
+ // PSC3 serial port A aka ttyPSC0
+ [EMAIL PROTECTED] {
+ device_type = "serial";
+ compatible = "fsl,mpc5121-psc-uart";
+ port-number = <0>; // Logical port assignment
+ cell-index = <3>;
+ reg = <11300 100>;
+ interrupts = <28 8>; // actually the fifo irq
+ interrupt-parent = < &ipic >;
+ };
+
+ // PSC4 serial port B aka ttyPSC1
+ [EMAIL PROTECTED] {
+ device_type = "serial";
+ compatible = "fsl,mpc5121-psc-uart";
+ port-number = <1>; // Logical port assignment
+ cell-index = <4>;
+ reg = <11400 100>;
+ interrupts = <28 8>; // actually the fifo irq
+ interrupt-parent = < &ipic >;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "fsl,mpc512x-psc-fifo";
+ reg = <11f00 100>;
+ interrupts = <28 8>;
+ interrupt-parent = < &ipic >;
+ };
+ };
+};
--
1.5.3.5.726.g41a7a
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