On Mon, Feb 06, 2017 at 10:22:01AM +1100, Benjamin Herrenschmidt wrote: > > On the plus side, that means that the values are guaranteed not > > to be core-specific. On the minus side, it means that its count rate is > > lower, and it's sufficiently "distant" that accessing it is somewhat more > > expensive. > > Right so there are various configuration options and ways to feed the timebase > to PowerPC chips depending on the generation and manufacturer. On the old > 32-bit chips, typically it was either a divisor of the bus frequency or > externally clocked. Apple typically used the latter.
On all 6xx and most 7xx/7xxx it is 1:4 of the bus clock. And on the newer machines the clock chip uses clock spreading. So you then cannot calibrate with a dumb fast routine (the time base ticks pretty slow anyhow, you cannot calibrate any fast if you want decent results; but with clock spreading you either have to measure for many seconds, or you need to find the period of the spreading and work with that). > > The PowerPC architecture permits the timebase frequency to be variable, > > but I'm not aware of any implementations that take advantage of that. > > I think it's pretty much accepted that this would be a very bad idea > and no implementation did it. See above. > > The > > Motorola 32-bit implementations in general run it on the "bus clock", > > which is independent of processor-clock multipliers, and is also common > > across processor chips in systems with more than one. > > There's also a TBEN external pin iirc which can be used to feed it. Some implementations have an MSR bit to stop the TB as well (7450 for example). Segher
