Benjamin Herrenschmidt <b...@kernel.crashing.org> writes:
> diff --git a/arch/powerpc/include/uapi/asm/auxvec.h > b/arch/powerpc/include/uapi/asm/auxvec.h > index ce17d2c..79183d2 100644 > --- a/arch/powerpc/include/uapi/asm/auxvec.h > +++ b/arch/powerpc/include/uapi/asm/auxvec.h > @@ -16,6 +16,37 @@ > */ > #define AT_SYSINFO_EHDR 33 > > -#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */ > +/* > + * AT_*CACHEBSIZE above represent the cache *block* size which is > + * the size that is affected by the cache management instructions. > + * > + * It doesn't nececssarily matches the cache *line* size which is > + * more of a performance tuning hint. Additionally the latter can > + * be different for the different cache levels. > + * > + * The set of entries below represent more extensive information > + * about the caches, in the form of two entry per cache type, > + * one entry containing the cache size in bytes, and the other > + * containing the cache line size in bytes in the bottom 16 bits > + * and the cache associativity in the next 16 bits. > + * > + * The associativity is such that if N is the 16-bit value, the > + * cache is N way set associative. A value if 0xffff means fully > + * associative, a value of 1 means directly mapped. > + * > + * For all these fields, a value of 0 means that the information > + * is not known. > + */ > + > +#define AT_L1I_CACHESIZE 40 > +#define AT_L1I_CACHESHAPE 41 > +#define AT_L1D_CACHESIZE 42 > +#define AT_L1D_CACHESHAPE 43 > +#define AT_L2_CACHESIZE 44 > +#define AT_L2_CACHESHAPE 45 > +#define AT_L3_CACHESIZE 46 > +#define AT_L3_CACHESHAPE 47 These names will clash with the other ones defined by alpha and sh: /* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains log2 of line size; mask those to get cache size. */ #define AT_L1I_CACHESHAPE 34 #define AT_L1D_CACHESHAPE 35 #define AT_L2_CACHESHAPE 36 #define AT_L3_CACHESHAPE 37 -- Tulio Magno
