"Shreyas B. Prabhu" <shre...@linux.vnet.ibm.com> writes: > POWER ISA v3 defines a new idle processor core mechanism. In summary, > a) new instruction named stop is added. > b) new per thread SPR named PSSCR is added which controls the behavior > of stop instruction. > > Supported idle states and value to be written to PSSCR register to enter > any idle state is exposed via ibm,cpu-idle-state-names and > ibm,cpu-idle-state-psscr respectively. To enter an idle state, > platform provided power_stop() needs to be invoked with the appropriate > PSSCR value. > > This patch adds support for this new mechanism in cpuidle powernv driver. > > Cc: Rafael J. Wysocki <rafael.j.wyso...@intel.com> > Cc: Daniel Lezcano <daniel.lezc...@linaro.org> > Cc: Rob Herring <robh...@kernel.org> > Cc: Lorenzo Pieralisi <lorenzo.pieral...@arm.com> > Cc: linux...@vger.kernel.org
Rafael/Daniel do you guys want to ack or nack this? I'll take silence as "not bothered" and merge the whole series via the powerpc tree. cheers _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
