On Thu, 2016-09-06 at 02:31:09 UTC, Michael Neuling wrote: > From: Jack Miller <j...@codezen.org> > > This enables new registers, LMRR and LMSER, that can trigger an EBB in > userspace code when a monitored load (via the new ldmx instruction) > loads memory from a monitored space. This facility is controlled by a > new FSCR bit, LM. > > This patch disables the FSCR LM control bit on task init and enables > that bit when a load monitor facility unavailable exception is taken > for using it. On context switch, this bit is then used to determine > whether the two relevant registers are saved and restored. This is > done lazily for performance reasons. > > Signed-off-by: Jack Miller <j...@codezen.org> > Signed-off-by: Michael Neuling <mi...@neuling.org>
Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/bd3ea317fddfd0f2044f94bed2 cheers _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
