"Aneesh Kumar K.V" <aneesh.ku...@linux.vnet.ibm.com> writes:
> Hello, > > This series mostly consisting of code movement. One new thing added in this > series > is to switch book3s 64 to 4 level page table. The changes are done to > accomodate > the upcoming new memory model in future powerpc chips. The details of the new > MMU model can be found at > > http://ibm.biz/power-isa3 (Needs registration). I am including a summary of > the changes below. > > ISA 3.0 adds support for the radix tree style of MMU with full > virtualization and related control mechanisms that manage its > coexistence with the HPT. Radix-using operating systems will > manage their own translation tables instead of relying on hcalls. > > Radix style MMU model requires us to do a 4 level page table > with 64K and 4K page size. The table index size different page size > is listed below > > PGD -> 13 bits > PUD -> 9 (1G hugepage) > PMD -> 9 (2M huge page) > PTE -> 5 (for 64k), 9 (for 4k) > > We also require the page table to be in big endian format. > > Changes from V3: > * rebase on top of PTE bits movement patch series > * Drop all the hash linux abstraction patches > * Keep only 4 level table and other code movement patches. > > Changes from V2: > * rebase to latest kernel > * Update commit messages > * address review comments > > Changes from V1: > * move patches adding helpers to the next series > > > NOTE: > This is lightly tested. Right now 4K linux page size is what is being > tested. Once that is done > I will have to do 64K linux page size tests. > Tested the below tests with 4K page size and 64K page size * libhugetlbfs test * ltp mm tests * kernel build in loop (testing thp collapse and split) -aneesh _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
