On Fri, 19 Oct 2007, Benjamin Herrenschmidt wrote:
>
> The barrier would guarantee that ioc->active (and in fact the write to
> the chip too above) are globally visible
No, it doesn't really guarantee that.
The thing is, there is no such thing as "globally visible".
There is a "ordering of visibility wrt CPU's", but it's not global, it's
quite potentially per-CPU. So a barrier on one CPU doesn't guarantee
anything at all without a barrier on the *other* CPU.
That said, the interrupt handling itself contains various barriers on the
CPU's that receive interrupts, thanks to the spinlocking. But I do agree
with Herbert that adding a "smb_mb()" is certainly in no way "obviously
correct", because it doesn't talk about what the other side does wrt
barriers and that word in memory.
Linus
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