Scott Wood writes: > Previously, the TLB miss handlers assumed that pages above KERNELBASE are > always present and read/write. This assumption is false in the case of > CONFIG_DEBUG_PAGEALLOC.
> blt+ 112f > + mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ > + rlwinm r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ > lis r2,[EMAIL PROTECTED] /* if kernel address, use */ > addi r2,r2,[EMAIL PROTECTED] /* kernel page table */ > - mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ > - rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ I don't see that just moving those two lines up changes anything. If you turned the rlwinm into an rlwimi (as you did in the DataStoreTLBMiss case) then it might make more sense. Is this just an oversight? Paul. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
