>> #define mb() __asm__ __volatile__ ("sync" : : : "memory")
>> -#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : :
>> "memory")
>> +#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
>> #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
>> #define read_barrier_depends() do { } while(0)
>>
>> @@ -42,7 +42,7 @@
>> #ifdef __KERNEL__
>> #ifdef CONFIG_SMP
>> #define smp_mb() mb()
>> -#define smp_rmb() rmb()
>> +#define smp_rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : :
>> "memory")
>> #define smp_wmb() eieio()
>> #define smp_read_barrier_depends() read_barrier_depends()
>> #else
>
> I had to think about this one for awhile. It looks at first glance to
> be the right
> thing to do. But I do wonder how long rmb() has been lwsync
Since the {ppc,ppc64} -> powerpc merge.
> and if as a practical matter that has caused any problems?
It has not as far as I know.
> If this isn't causing any problems maybe there
> is some loigic we are overlooking?
The I/O accessor functions enforce the necessary ordering
already I believe.
Segher
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