On Thu, 2007-08-02 at 15:56 +1000, Michael Neuling wrote: > > But even in the case of a checkpoint restart, the ordering will be > preserved as the NIA we get as part of the checkpoint will have all > previous instructions complete and none of the following instructions > started.
Instruction completion isn't enough to ensure storage ordering. The stores may well be complete but the data still in separate store queues. > So I guess the questions is, does PHYP even need to access the shadow > buffer of another CPU, while that other CPU is in flight. I'm not > sure > that they can as they can't read the entire buffer atomically if the > target CPU is still active. So PHYP must stop instructions on the > target CPU, before it reads it's shadow buffer. Hence no ordering > problems. > > I should probably talk to some PHYP guys to confirm, but i think we > can > remove all the barriers when writing to the shadow buffer Bah, just keep then in, eieio's won't hurt much and it doesn't look like a critically hot code path. Ben. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
